Capt Leleia Hsia, Assistant Professor of Electrical Engineering

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Contact:
Comm: 937-255-3636 x4705
DSN: 986-3636 x4705
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Education

Ph.D., Electrical Engineering, Air Force Institute of Technology, 2021

M.S., Electrical Engineering, Air Force Institute of Technology, 2015

B.S., Electrical Engineering, The Citadel, 2013

B.A., Modern Languages - Spanish, The Citadel, 2013

Publications

L. A. Hsia, “Physically Unclonable Characteristics for Verification of Transmon-Based Quantum Computers,” Ph.D. Dissertation, Dept. Electrical and Computer Engineering, Air Force Institute of Technology, Wright-Patterson Air Force Base, Ohio, 2021.

L. A. Hsia, L. D. Merkle, D. E. Weeks, G. Vernizzi, M. Y. Lanzerotti, D. Langley, “Physically Unclonable Characteristics for Verification of Transmon-Based Quantum Computers,” Proceedings of 2020 Government Microcircuit Applications and Critical Technology Conference, San Diego, CA, March 2020.

L. A. Hsia, L. D. Merkle, G. Vernizzi, M. Y. Lanzerotti, D. Langley, “On Classical Hardware Verification and Security Techniques for Quantum Computing Systems,” Proceedings of 2019 Government Microcircuit Applications and Critical Technology Conference, Albuquerque, NM, March 2019.

L. A. Hsia, G. Vernizzi, M. Y. Lanzerotti, D. Langley, “Sampling Iso-Functional Signal Switches in Library Circuits for Microelectronics Verification with Topological Constraints,” National Aerospace & Electronics Conference (NAECON), Dayton, OH, June 2017.

L. A. Hsia, G. Vernizzi, M. Y. Lanzerotti, D. Langley, “Building a Library for Microelectronics Verification with Topological Constraints,” Proceedings of 2017 Government Microcircuit Applications and Critical Technology Conference, Reno, NV, March 2017.

L. A. Hsia, “Gate-Level Commercial Microelectronics Verification with Standard Cell Recognition,” M.S. thesis, Dept. Electrical and Computer Engineering, Air Force Institute of Technology, Wright-Patterson Air Force Base, Ohio, 2015.

L. A. Hsia, G. Vernizzi, M. Y. Lanzerotti, D. Langley, M. K. Seery, L. Orlando, “Topological Constraints of Gate-Level Circuits Obtained Through Standard Cell Recognition (SCR),” National Aerospace & Electronics Conference (NAECON), Dayton, OH, June 2015.

L. A. Hsia, M. K. Seery, M. Y. Lanzerotti, L. Orlando, “Standard Cell Recognition Applied to Gate-Level Commercial Microelectronics Verification,” Proceedings of 2015 Government Microcircuit Applications and Critical Technology Conference, St. Louis, MO, Mar 2015.

L. A. Hsia, M. K. Seery, M. Y. Lanzerotti, L. Orlando, “Gate-Level Commercial Microelectronics Verification with Standard Cell Recognition,” National Aerospace & Electronics Conference (NAECON), Dayton, OH, June 2014.

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